Generally, an artificial neural network is composed of many simple processing elements called neurons or neurodes, that typically do little more than take a weighted sum of all its inputs. The neural network responds simultaneously to the inputs presented to it. The result is not stored in a specific memory location, but consists of the overall state of the network after it has reached some equilibrium condition.
In the neural network lexicon, the term "self-organization" generally refers to the ability of some networks to learn without being given the correct answer for an input pattern. One such self-organizing network is utilized in the Kohonen learning system. A Kohonen self-organizing network is surprisingly simple at first glance and consists of a single layer of neurodes which are connected within the layer and the outside world.
In practice, an input pattern is depicted as a plurality of input vectors, or simply "inputs" for this discussion. In a digital network, an input pattern defined by a convenient plurality of data bits (e.g. 8, 16, etc.) is presented to the Kohonen network. Each neurode in the Kohonen layer receives the input pattern and computes a similarity measurement of a weight stored in the neurode (having a similar number of bits) with the input pattern, which is basically the distance between the stored weight vector and the input pattern vector. The neurodes then compete for the privilege of learning with the neurode having the closest similarity measurement being declared the winner. In an original iteration several neurodes in an area with at least one neurod having close similarity measurements are allowed to learn and, ultimately, one neurode is the winner and is allowed to output a signal.
Generally, in a Kohonen neurode a random access memory (RAM) is used to store the plurality of bits representative of one of the stored weights and the function of determining the similarity measurement is performed by various digital components (i.e. multipliers, subtracters, adders, etc.). The various digital components are relatively simple and inexpensive, because they are normally time shared, while the RAM required to store the data bits is a major expense in the complete system. Further, as the storage capacity of the RAM is increased in order to increase the number of data bits being stored so as to increase the definition of the weight vector, the cost and size of the RAM increases dramatically.
Accordingly, it would be advantageous to increase the precision of the processing elements without substantially increasing the cost and size thereof.
It is a purpose of the present invention to provide a new and improved method of generating adaptive weight adjustments with extended precision.
It is another purpose of the present invention to provide a new and improved processing element for generating adaptive weight adjustments with extended precision.
It is yet another purpose of the present invention to provide a new and improved method of generating adaptive weight adjustments with extended precision without increasing the size of the RAM included therein.
It is still another purpose of the present invention to provide a new and improved processing element for generating adaptive weight adjustments with extended precision having very little increase in cost and size.